One-hot state machine design for FPGAs by Steve Golson
Abstract: One-hot state machines use one flop per state. They are particularly suited to today’s register-rich FPGA architectures. This paper will discuss the advantages of one-hot state machines including ease of design, simple timing analysis, and high clock rates. An SBus master/slave interface will be used as a design example. VHDL and Verilog coding styles will be discussed.
Most of this is pretty dated.