State machine design techniques for Verilog and VHDL by Steve Golson
Abstract: Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles will be presented. Different methodologies will be compared using real-world examples.
This has been a very popular paper, although it really needs to be updated.