Push-button synthesis or, using dc_perl to do_the_right_thing by Kurt Baty and Steve Golson
Abstract: We have developed a methodology to automatically synthesize large hierarchical designs. This methodology combines the advantages of bottom-up compilation with top-down rebudgeting.
Starting with only the Verilog source code, all required makefiles, synthesis scripts, and constraint files are automatically derived. An overconstraining leaf module time-budgeting method is used for initial synthesis.
For subsequent synthesis runs, a top-level constraint file (perhaps manually generated) is used to automatically create constraints for leaf modules. Timing information is extracted from top-level timing reports. True timing budgets can be generated while avoiding the limitations of characterize.
This won the Best Paper Award.
My SNUG 1997 paper introduced dc_perl. Here’s the updated version of the dc_perl script that includes the do_the_right_thing command.
dc_perl is very simple and very fragile. It was mostly a proof of concept. If you are considering using Perl and Design Compiler (or any other Synopsys tool) I recommend you have a look at Jeff Solomon’s excellent Perl module SPP.
Also at this conference I appeared on a panel discussion titled The Missing Links in EDA. I talked at some length about why running high-end EDA tools on Windows NT is such a bad idea.