Team Geriatric Guys with Gates Participates in the VDF Design Competition: It’s All About Speed and Power by Kurt Baty and Steve Golson
Abstract: VDF Alliance has created a design competition to find the fastest verifiable delay function (VDF) implementation. Kurt and Steve have entered as a team! We start with a brief introduction to VDFs and their use in blockchains and elsewhere, followed by a discussion of wide-bit arithmetic and the challenges of implementing low-latency VDFs in a Xilinx FPGA. That leads us into an in-depth analysis of power and the problems we encountered on AWS F1 systems. Next we will review the results from the FPGA phases of the competition and how our Team GGG has fared. Finally we will introduce the next ASIC phase of the competition, coming later in 2020.
Our slides are available here. Details of our submitted designs are linked below: