Author: sgolson
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1997 Design Automation Conference (DAC 1997)
The road ahead in CPLD & FPGA design methodology (panel) I was the token ASIC designer on this panel. Here are the slides I presented.
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1997 Synopsys Users Group Conference (SNUG San Jose 1997)
dc_perl: Enhancing dc_shell using a Perl wrapper by Steve Golson Abstract: Is there a command that you wish dc_shell had? By using the Perl interpreter as a “wrapper” around dc_shell, powerful extensions to dc_shell can be created. dc_shell commands can be generated by Perl, and the results analyzed by Perl in real time (not post-processed).…
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1996
Comet authority Fred Whipple has dubbed them “dirty snowballs”—small bodies of ice and dust only a few kilometers across. On close approach to the sun this frozen material vaporizes and streams away from the comet forming a tail millions of kilometers long. Charged particles emitted by the sun travel outward at hundreds of kilometers per…
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1995
What we call moonlight is really just sunlight reflected from the surface of the moon. It is white light; it has the same color balance as sunlight. Our eyes are poorly suited to detecting colors at low light levels, but a long exposure photograph using moonlight reveals the true colors of autumn leaves. As the earth rotates the…
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1995 Synopsys Users Group Conference (SNUG San Jose 1995)
My Favorite dc_shell Tricks by Steve Golson Abstract: You can make dc_shell do amazing and wonderful things. Many of the complaints and workarounds explored in this paper have been addressed in later versions of Design Compiler. Tcl is a huge improvement as well. Here is the buffer tree insertion script buf.ss that was described in…
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1994
An annular eclipse occurs when the moon comes between the earth and the sun, however the moon appears smaller than the sun and thus never completely blocks it. At maximum coverage observers on the eclipse track will see a ring of sunlight around the moon. The name comes from the Latin word annulus meaning ‘ring.’ Annular eclipse…
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1994 Synopsys Users Group Conference (SNUG San Jose 1994)
State machine design techniques for Verilog and VHDL by Steve Golson Abstract: Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles will be presented. Different methodologies will be…
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3rd PLD Design Conference, Santa Clara CA (PLDcon 1993)
One-hot state machine design for FPGAs by Steve Golson Abstract: One-hot state machines use one flop per state. They are particularly suited to today’s register-rich FPGA architectures. This paper will discuss the advantages of one-hot state machines including ease of design, simple timing analysis, and high clock rates. An SBus master/slave interface will be used…