Language Wars in the 21st Century: Verilog versus VHDL – Revisited by Steve Golson and Leah Clark
Abstract: Back in the late 20th century, the VHDL versus Verilog debate was compared to a religious war that neither side could win. At various times, knowledgeable industry leaders have predicted that each HDL would prevail, but it seems we still live in a bilingual world. Is there still a language war?
In order to understand this conflict, we must first study where these languages came from and how they have evolved. Perhaps they aren’t interchangeable, but instead can coexist, providing the right tool for the right job as needed. How does supporting more than one HDL affect your Synopsys flow? Has SystemVerilog changed the landscape?
Whether we continue to live in a dual-language world, or are approaching a time when one language will dominate, there are ramifications to be considered. We will discuss these concerns and much more, and hopefully we will answer the question once and for all of which HDL is “the winner”.