Verilog HDL and its ancestors and descendants by Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, and Simon Davidmann.
Presented at The Fourth ACM SIGPLAN History of Programming Language Conference (HOPL IV), June 20–22, 2021.
Published in Proceedings of the ACM on Programming Languages, Vol. 4, No. HOPL, Article 87, June 2020, 90 pages.
This is a superlative history of the Verilog and SystemVerilog languages, written by the original creators of HILO, Verilog, and Superlog. I was pleased to be invited to help, and bring a synthesis perspective to the mix.
Abstract:
This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniques have transformed into textual register-transfer level (RTL) descriptions written in Verilog. As of 2018 about 80% of integrated circuit design teams worldwide use Verilog and its compatible descendant SystemVerilog.