Papers and Presentations by Steve Golson

Lawyers, Games and Money
General Computer Goes to Court
by Steve Golson

Here’s the description from the California Extreme website:

A look behind the scenes of the many legal disputes involving GCC, including:

• Atari’s 1981 lawsuit over Super Missile Attack, GCC’s enhancement kit for Missile Command
• licensing Crazy Otto to Midway, which led to Ms. Pac-Man
• character trademarks and royalties
• forty years of controversies about Ms. Pac-Man and Jr. Pac-Man

This talk was recorded, and should be available on YouTube soon. Here are my slides (sorry, no embedded video).

The Mysteries Of Ms. Pac-Man

Here’s the description from the PRGE website:

Join some of the team who helped create Ms. Pac-Man in this panel discussion. Hear the weird and unusual tales of video game’s First Lady, Ms. Pac-Man, celebrating her 40th birthday! Wild stories about lawsuits with Atari, the Chicago connection, Crazy Otto, and more! Panel discussion with creators Kevin Curran and Steve Golson, moderated by Pac-Man: Birth of an Icon co-author Tim Lapetino.

It was great working again with old friend Kevin Curran! And buy Tim’s book Pac-Man: Birth of an Icon, it is wonderful.

Thanks to Seattle Retro Guy you can watch the talk here:

Verilog HDL and its ancestors and descendants by Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, and Simon Davidmann.

Presented at The Fourth ACM SIGPLAN History of Programming Language Conference (HOPL IV), June 20–22, 2021. Presentation video available here.

Published in Proceedings of the ACM on Programming Languages, Vol. 4, No. HOPL, Article 87, June 2020, 90 pages.

This is a superlative history of the Verilog and SystemVerilog languages, written by the original creators of HILO, Verilog, and Superlog. I was pleased to be invited to help, and bring a synthesis perspective to the mix.

Abstract:

This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniques have transformed into textual register-transfer level (RTL) descriptions written in Verilog. As of 2018 about 80% of integrated circuit design teams worldwide use Verilog and its compatible descendant SystemVerilog.

Ms. Pac-Man, Food Fight, Quantum, and the Rest: Arcade Game Design at GCC with Steve Golson

Fun recollections from the game development days at General Computer. Here are my slides.

Many thanks to my good friends at ACAM for inviting me to present this talk.

Video Games Then and Now: An Entrepreneuring Journey by Steve Golson

I was honored to be keynote speaker at the New Hampshire High Tech Council 2018 Entrepreneur of the Year Awards. Matt Albuquerque was the well-deserved winner this year. And a special Lifetime Achievement award was given to the great Ralph Baer. It was a wonderful evening celebrating games and entrepreneurs!

The Atari 7800 ProSystem with Steve Golson

I got to talk again about the amazing 7800.

Thanks to Hans Reutter, you can watch this presentation here.

ACAM Presents: Steve Golson, The 7800 ProSystem

Here’s the description from the ReplayFX website:

The Atari 7800 ProSystem console was not designed by Atari. The people of General Computer Corporation (GCC) of Massachusetts created this console for Atari with an intended release in 1984, but it did not officially hit the market until 1986. Steve Golson, one of the original developers of Ms. Pac-Man at GCC, also worked on the Maria graphics chip for the Atari 7800. Join Steve as he discusses the creation, history & legacy of this amazing backwards-compatible gaming device.

Steve worked for General Computer of Cambridge, MA. from 1981 through 1985. He created the hardware design for GCC’s arcade enhancement kits Super Missile Attack and Ms. Pac-Man. Steve also contributed to various other arcade game projects at GCC such as Atari’s Charley Chuck’s Food Fight. Steve is a frequent contributor to ACAM’s education projects, and participates with ACAM at gaming events on a regular basis.

Language Wars in the 21st Century: Verilog versus VHDL – Revisited by Steve Golson and Leah Clark

Abstract: Back in the late 20th century, the VHDL versus Verilog debate was compared to a religious war that neither side could win. At various times, knowledgeable industry leaders have predicted that each HDL would prevail, but it seems we still live in a bilingual world. Is there still a language war?

In order to understand this conflict, we must first study where these languages came from and how they have evolved. Perhaps they aren’t interchangeable, but instead can coexist, providing the right tool for the right job as needed. How does supporting more than one HDL affect your Synopsys flow? Has SystemVerilog changed the landscape?

Whether we continue to live in a dual-language world, or are approaching a time when one language will dominate, there are ramifications to be considered. We will discuss these concerns and much more, and hopefully we will answer the question once and for all of which HDL is “the winner”.

ACAM Presents Steve Golson: From Crazy Otto to Ms. Pac-Man

Here’s the description from the ReplayFX website:

Steve Golson, one of the original developers of Ms. Pac-Man at General Computer Corporation (GCC), will recount little-known stories about the creation of this iconic 1982 game. How and why did it transform from Crazy Otto to Ms. Pac-Man? Using source code and graphics ROMs extracted from his 30-year-old 8″ floppy archives, Steve will show the evolution of game play and character design. Steve will also discuss GCC’s first product Super Missile Attack, including the SMA 2.0 version created during GCC’s lawsuit with Atari.

Steve worked for General Computer of Cambridge, MA. from 1981 through 1985. Steve performed the hardware design for GCC’s arcade enhancement kits Super Missile Attack and Ms. Pac-Man. Steve also worked on the Maria graphics chip for the Atari 7800 ProSystem home console, & was a contributor to various other arcade game projects at GCC such as Atari’s Charley Chuck’s Food Fight. Steve is a frequent contributor to ACAM’s education projects, and participates with ACAM at gaming events on a regular basis.

It’s always a pleasure working with Mike Stulir and the other great folks at American Classic Arcade Museum (ACAM). Please visit!

Crazy Otto: Then and Now by Brendon “Jr. Pac” Parker with Steve Golson

A description of this talk from the California Extreme website:

Fourteen year-old Brendon “Jr. Pac” will give details on what inspired him to begin collecting arcade games at the young age of eleven. After years of skepticism from adult collectors, and lots of hard work, he has earned a good standing in the collecting community.

Brendon will discuss his most prized project, a full-cabinet recreation of what Crazy Otto might have been if it had actually come onto the market. Utilizing modern-day technology, he has faithfully recreated the original Crazy Otto game and designed a complete cabinet in the theme of the classic Ms. Pac-Man.

Steve Golson, one of the original designers of Crazy Otto/Ms. Pac-Man in 1981, will talk about the development and history of this iconic game.

Brendon’s Crazy Otto machine will be available for play.

Here’s a nice story at Motherboard that mentions Brendon (and me). And another story about Brendon.

And here’s a YouTube video of the talk:

Synchronization and Metastability by Steve Golson

Abstract: The phenomenon of metastability is inherent in clocked digital logic. Many techniques have been presented for minimizing metastability, both for crossing clock domains, and for handling asynchronous inputs. Some of these “best practices” have unexpected weaknesses and must be used carefully, particularly at smaller process nodes. This paper will explore these shortcomings and suggest alternative schemes that are more robust. A PrimeTime methodology for verifying multi-clock designs will be presented.

This won the Best Paper Award. Here are my slides.

I also presented this paper at Boston SNUG in September 2014.

Thanks to the nice folks at Synopsys who recorded my talk in Santa Clara, you can watch the slides while you listen to my talk (sorry about the poor audio):

Push Button: From Crazy Otto to Ms. Pac-Man by Steve Golson

This is (mostly) a repeat of my California Extreme talk from 2012, but in addition I discuss other GCC arcade projects such as Jr. Pac-Man, Quantum, Food Fight, and Nightmare. Also I talk about the development environment at GCC. Many thanks to MIT Game Lab for making this available online.

Doug Macrae is in the audience and he contributed some wonderful insights and anecdotes. Listen to the Q&A and you can hear my discourse on copyright infringement and intellectual property.

History of Atari 7800 ProSystem Development at General Computer by Steve Golson

Summary: A brief history of General Computer and its leading role in the development of the Atari 7800 ProSystem. Also a review of GCC’s other products for Atari home game consoles and computers.

Thanks to Irish Nerd Life you can watch part of this on YouTube. Hopefully someday I can put up the full talk.

From Crazy Otto to Ms. Pac-Man by Steve Golson

Here’s the description from the conference website:

Ms. Pac-Man was released in early 1982, so she turns thirty this year. Steve Golson, one of the original developers of Ms. Pac-Man at General Computer, will recount little-known stories about the creation of the game. How and why did it transform from Crazy Otto to Ms. Pac-Man? Using source code and graphics ROMs freshly extracted from his 30-year-old 8″ floppy archives, Steve will show the evolution of game play and character design.

Steve will also discuss GCC’s first product Super Missile Attack, and will reveal the SMA 2.0 version created during GCC’s lawsuit with Atari.

Crazy Otto and Super Missile Attack 2.0 will be available for play.

Errata: A former Atari employee assures me that the link between PDP11 and black/blue box was not paper tape; most likely it was a serial line. If I am wrong, please accept my apologies. I stand corrected. My slide 17 was based on two interviews I found, one with Dave Theurer. Nevertheless I feel my point is still valid: our development environment at GCC was much more interactive than what Atari used for Missile Command.

Here are the slides as a QuickTime movie and as PDF. The PDF version does not have the cool game play screenshots.

Thanks to kitkatdady1 who recorded this and made it available on YouTube: part 1 and part 2. Also many thanks to Trevor Brown who recorded me after the talk doing some show-and-tell with Super Missile Attack and Crazy Otto artifacts.

Consistent Timing Constraints with PrimeTime by Steve Golson

Abstract: Physical implementation tools are usually timing-driven. They require timing constraints for reliable, repeatable, and successful operation. Generating and verifying these constraints is a familiar yet sometimes tedious task for the physical implementation engineer.

We introduce the idea of consistent timing constraints and show how PrimeTime can be used to create and manage timing constraint files needed for all other implementation tools, from synthesis to place-and-route to final chip finishing.

Here are the slides.

Flow Engineering for Physical Implementation: Theory and Practice by Steve Golson and Pete Churchill

Abstract: EDA tools are never used in isolation. Rather, multiple tools are combined into a sequence called a flow. Furthermore an elaborate infrastructure is required to support and enable flow execution. This flow infrastructure includes directory organization, configuration management, compute servers, desktop machines, job control, license administration, dependency management, operating systems, team communication, error reporting, and libraries of all sorts. Oh, and of course the EDA tools themselves. While EDA tools come with documentation and user guides, and many of the components of the flow infrastructure have standalone documentation, there is virtually no manual or reference guide or checklist available to aid in the creation and improvement of a flow. Join two veteran consultants, each with over 20 years experience in IC design, as we discuss the theory and practice of flow engineering: the design of flow infrastructure and the flows themselves.

Here are the slides as PDF and PowerPoint. It may be hard to follow when you don’t have Pete and me making the presentation, and you’ll probably miss the jokes. Also there are some provocative statements (slide 28 comes to mind). You have to hear the talk to understand the context. Really, we love EDA tools.

Thanks to the Wayback Machine here is an archive of the flowmaker.info website.

The Human ECO Compiler by Steve Golson

Abstract: Engineering Change Orders or ECOs are all too prevalent in ASIC design. Unfortunately there are few tools that directly support these “last minute” changes to a design. So it’s left to us humans to figure out a solution.

This paper will cover the ad hoc solutions that have been developed for implementing ECOs. Topics to be covered:

• basic definitions: the types of ECOs
• where in the flow to make the change
• advanced netlist dissection techniques
• implementing large ECOs using thousands of gates
• equivalence checking: your best friend
• back-end issues
• why ECOs are really a management problem, and how to deal with it

This won the Best Paper Award.

I gave this paper again at Boston SNUG in September 2004, and won Best Paper there, too! (Now the rules are different so you can’t win twice for the same paper any more…)

Asynchronous & Synchronous Reset Design Techniques – Part Deux by Clifford E. Cummings, Don Mills, and Steve Golson

Abstract: This paper will investigate the pros and cons of synchronous and asynchronous resets. It will then look at usage of each type of reset followed by recommendations for proper usage of each type.

I recommend you use synchronous resets as much as possible.

The Future of ASIC Design(ers) by Steve Golson

This year I was honored to be invited as Guest Speaker, and these are the slides from the presentation I gave. It’s a bit harder to follow when you don’t have me talking to each slide, but perhaps you can still get some of the jokes 🙂 The astute reader will note some overlap with my SNUG 2000 presentation. I prefer to call it design reuse.

Thanks to John Cooley who recorded this spontaneous remark from my presentation:

I don’t know what kind of HDL most ASIC designers will use in the year 2010, but it will be called Verilog.
— Steve Golson, guest speaker at SNUG ’02

Looks like I was right!

Panel: The Value of Verification

Abstract: The debate over verification continues unabated over how critical a role it plays in the overall design process. In some circles, it is viewed as essential and valuable. Even so, there are questions over which verification tools are necessary and what tools work. Project teams need to determine whether to spend more time on verification, or less time. As a result, they must evaluate the relative contribution to a design’s success made by design engineers versus verification engineers. Some design stalwarts wonder if an entire team to correct the mistakes of the designer isn’t overkill. Still others wonder just how interesting or creative the role or verification engineer really is.

Should the role of verification engineer be a career goal? When a project team ramps up, who’s hired first, designers or verification engineers? The panel will take a hard look at the true value of verification and offer some candid answers.

I was the token ”design engineer” on the panel. One of these days I’ll write down my thoughts about architecture, design, and verification.

A Comparison of Hierarchical Compile Strategies by Steve Golson

Abstract: A wealth of new hierarchical compile strategies have become available in the last few years. This paper will compare area, speed, and compile time for several large designs using a variety of hierarchical compile strategies: top-down compile, top-down simple compile, bottom-up with default constraints, bottom-up with hand-crafted constraints, and ACS (Automated Chip Synthesis).

You can download a tarball of all of the scripts, constraint files, and Makefiles described in the paper.

Get more information about the picoJava-II design from Sun Microsystems.

Here are Perl scripts for doing scatter_plots and ratio_plots. These scripts take timing reports from Synopsys Design Compiler and generate commands for gnuplot.

My SNUG 1999 paper used similar plotting techniques.

Levels of Abstraction: The History of Custom MOS Design by Steve Golson

For the Tenth SNUG in 2000, Kurt Baty organized a panel discussion that reviewed progress in synthesis, simulation, and EDA tools in general over the past decade. Here are the slides from my presentation covering the history and possible future of ASIC design.

Resistance is Futile! Building Better Wireload Models by Steve Golson

Abstract: Wireload models are like the weather. Many people talk about them, but not many people do anything about them! This paper will explore some of the myths and realities of wireload models:

• why wireload models are important, and why nobody understands them
• why your intuition is wrong
• why you shouldn’t trust your silicon vendor
• why floorplanning sometimes doesn’t matter
• why having an accurate wireload model is a bad idea

A technique for measuring the quality of wireload models will be described. Real-world results will be discussed. Cool graphics will be shown. A desperate plea for future work will be given.

This won the Best Paper Award. Yes, that makes three years in a row.

Here are Perl scripts for doing scatter_plots and ratio_plots. These scripts take timing reports from Synopsys Design Compiler and generate commands for gnuplot.

My SNUG 2001 paper uses similar plotting techniques.

Push-button synthesis or, using dc_perl to do_the_right_thing by Kurt Baty and Steve Golson

Abstract: We have developed a methodology to automatically synthesize large hierarchical designs. This methodology combines the advantages of bottom-up compilation with top-down rebudgeting.

Starting with only the Verilog source code, all required makefiles, synthesis scripts, and constraint files are automatically derived. An overconstraining leaf module time-budgeting method is used for initial synthesis.

For subsequent synthesis runs, a top-level constraint file (perhaps manually generated) is used to automatically create constraints for leaf modules. Timing information is extracted from top-level timing reports. True timing budgets can be generated while avoiding the limitations of characterize.

This won the Best Paper Award.

My SNUG 1997 paper introduced dc_perl. Here’s the updated version of the dc_perl script that includes the do_the_right_thing command.

dc_perl is very simple and very fragile. It was mostly a proof of concept. If you are considering using Perl and Design Compiler (or any other Synopsys tool) I recommend you have a look at Jeff Solomon’s excellent Perl module SPP.

Also at this conference I appeared on a panel discussion titled The Missing Links in EDA. I talked at some length about why running high-end EDA tools on Windows NT is such a bad idea.

The road ahead in CPLD & FPGA design methodology (panel)

I was the token ASIC designer on this panel. Here are the slides I presented.

dc_perl: Enhancing dc_shell using a Perl wrapper by Steve Golson

Abstract: Is there a command that you wish dc_shell had?

By using the Perl interpreter as a “wrapper” around dc_shell, powerful extensions to dc_shell can be created. dc_shell commands can be generated by Perl, and the results analyzed by Perl in real time (not post-processed). Further dc_shell commands can be algorithmically generated by Perl based on the given results.

The user interface is just like dc_shell, but with user-defined extensions. This approach is particularly suited for complex synthesis problems that currently require lots of post-processing or tedious human analysis.

This won the Best Paper Award.

Here’s the original dc_perl distribution. See the SNUG 1998 paper for further work with dc_perl.

My Favorite dc_shell Tricks by Steve Golson

Abstract: You can make dc_shell do amazing and wonderful things.

Many of the complaints and workarounds explored in this paper have been addressed in later versions of Design Compiler. Tcl is a huge improvement as well.

Here is the buffer tree insertion script buf.ss that was described in my presentation at the conference.

State machine design techniques for Verilog and VHDL by Steve Golson

Abstract: Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles will be presented. Different methodologies will be compared using real-world examples.

This has been a very popular paper, although it really needs to be updated.

One-hot state machine design for FPGAs by Steve Golson

Abstract: One-hot state machines use one flop per state. They are particularly suited to today’s register-rich FPGA architectures. This paper will discuss the advantages of one-hot state machines including ease of design, simple timing analysis, and high clock rates. An SBus master/slave interface will be used as a design example. VHDL and Verilog coding styles will be discussed.

Most of this is pretty dated.

Pushing the Envelope by Steve Golson and Scott Griffith

Abstract: Use (and abuse) of VLSI Technology tools for full-custom design.

A 2K byte fully-associative cache memory with on-chip DRAM control by Scott Griffith and Steve Golson

Abstract: A 2Kbyte cache memory with on-chip DRAM control has been built. The fully-associative write-back write-allocate cache is organized as 128 lines by 16 bytes. The part directly connects to and controls an array of 1 Mb DRAMs forming a 4Mbyte parity-checked memory subsystem. Zero wait state operation of the Intel 80386 microprocessor at 25MHz is supported. Fabricated in a 2µ CMOS process, the 374×383 mil die contains 172K transistors.

The copyright for this paper is owned by IEEE so I can’t put a PDF here. A small number of reprints are available, and I’ll send you one if you email me and ask for it.

This chip project was codenamed Kali and was designed as the memory controller for the Sun 386i workstation (codename Roadrunner). It inspired John Sundman to write a wonderful award-winning hacker-thriller novel Acts of the Apostles.